Searching for the degree of optimal placement in high-availability multiprocessor systems with directed information transfer

This article addresses the search for the degree of optimality of process placement in high-availability clustered multiprocessor systems with directed information transfer. We introduce a hardware–software device that operationalizes a graph-based formulation: a weighted task-interaction graph is mapped onto the processor-topology graph, and the objective minimizes the total inter-processor link length defined as traffic weights multiplied by inter-module distances. The device combines a permutation generator with an evaluation unit operating over an electronic graph model while enforcing channel-bandwidth and processor-load constraints; early-stopping criteria are supported. Experimental evaluation on a fully connected four-processor configuration demonstrated a reduction in total link length from 450 to 320 arbitrary units (–29%) and a decrease in interaction intensity; aggregate system performance increased to 95% versus 80% under the baseline placement. The results indicate that the approach effectively relieves communication bottlenecks, reduces inter-processor traffic, and accelerates reconfiguration in real-time environments. Future work includes scaling to larger topologies, incorporating adaptive heuristics, and integrating with task-scheduling facilities to further enhance the resilience and predictability of high-availability computing platforms.